/****************************************************************************
 * FILE NAME: 		clock.h
 * 
 * PROJECT NAME: 	EGR330_Project
 * TEAM MEMBERS: 	Kevin Vermeer
 * 					Brandon Ross
 *					Tyler Selk
 *
 * 
 * CREATED: 		2 August 2011 (Brandon Ross)
 * LAST MODIFIED: 		
 * 
 * DESCRIPTION:		Handles functions necessary to operate clock
 ****************************************************************************/

/* HEADER GUARD */
#ifndef CLOCK_H
#define CLOCK_H

/***********************************************
 * REGISTER:	OSCCAL
 * NAME:		Oscillator Calibration Register
 * BIT FIELD:	Bit7 -> CAL7
 *				Bit6 -> CAL6
 *				Bit5 -> CAL5
 *				Bit4 -> CAL4
 *				Bit3 -> CAL3
 *				Bit2 -> CAL2
 *				Bit1 -> CAL1
 *				Bit0 -> CAL0
 ***********************************************/

/***********************************************
 * REGISTER:	CLKPR
 * NAME:		Clock Prescale Resister
 * BIT FIELD:	Bit7 -> CLKPCE
 *				Bit6 -> reserved
 *				Bit5 -> reserved
 *				Bit4 -> reserved
 *				Bit3 -> CLKPS3
 *				Bit2 -> CLKPS2
 *				Bit1 -> CLKPS1
 *				Bit0 -> CLKPS0
 ***********************************************/
#define CLK_MASK_CLKPSX 0x0F
#define CLK_POS_CLKPSX 0x00

#define CLK_PRESCALE_DF1 0x00
#define CLK_PRESCALE_DF2 0x01
#define CLK_PRESCALE_DF4 0x02
#define CLK_PRESCALE_DF8 0x03
#define CLK_PRESCALE_DF16 0x04
#define CLK_PRESCALE_DF32 0x05
#define CLK_PRESCALE_DF64 0x06
#define CLK_PRESCALE_DF128 0x07
#define CLK_PRESCALE_DF256 0x08

/*
 * DEFAULT INTERNAL CLOCK SOURCE: 8 MHz
 * DIVISION FACTOR 1:	8000 	kHz
 * DIVISION FACTOR 2:	4000 	kHz
 * DIVISION FACTOR 4:	2000 	kHz
 * DIVISION FACTOR 8:	1000 	kHz
 * DIVISION FACTOR 16:	500 	kHz
 * DIVISION FACTOR 32:	250 	kHz
 * DIVISION FACTOR 64:	125		kHz
 * DIVISION FACTOR 128:	62.5 	kHz
 * DIVISION FACTOR 256:	31.25	kHz
 */

void CLK_initialize(void);

#endif
